The invention relates generally to design systems for programmable logic devices. It finds particular application to a system and method for translating a report file of one logic device to a constraints file of another logic device so that a circuit design can be transferred from one logic device to the other logic device.
Different programmable logic vendors, in some cases, manufacture and sell pinout compatible devices. These are conventionally known as second sourced components. As an example, different vendors have certain device families that are generally pinout compatible between each other. Furthermore, there may be multiple families within a device family. For example, Altera offers 7000, 7000A, 7000AE, and 7000B series complex programmable logic devices (CPLD). Within each family, a range of devices, usually a subset of 32, 64, 128, 256, and 512 macrocell products, and a variety of packages is offered. Xilinx has a similar set of evolving families. Each vendor typically provides multiple products in the same package, usually with the same pinout. For example, several vendors provide both the 64 and 128 macrocell device in a 100 pin TQ package. These two devices have the same power and ground locations, so either device is a candidate for re-targeting to a second source.
Not all devices in each vendor""s device family are second sourced, and in some cases there may be minor differences in the pinout of the devices. While some devices are pinout compatible, they are typically not functionally identical. Even though there are functional differences, approximately 90% of circuit designs can be implemented in any of the vendor""s devices. Thus, they are generally considered second source components. However, since the devices are not functionally identical, each vendor supplies custom programmable logic design software to produce design files needed to program and use a selected logic device.
A designer uses the design software by describing a design in a supported format such as circuit schematics, VHDL, or Verilog. VHDL and Verilog are hardware description languages known in the art. VHDL stands for VHSIC Hardware Description Language, where VHSIC stands for very high speed integrated circuit. There are several other standard hardware description languages currently used in the art. Optionally, the designer can provide the design software with a constraints file which describes such information as the desired device and package to target, desired pinout locations for signals, and other hardware characteristics. The design software produces, in addition to programming files for programming the logic device, report files that contain device, product, package, pinout, and speed information that result from processing the circuit design. The report file and constraints file are not interchangeable by the design software of different vendors.
In prior systems, it has been very difficult for a designer to transfer a circuit design of one logic device to be used for another logic device of a different vendor. Manual analysis of device and package compatibility information was required and based on this information, the designer would manually edit the constraints file or device selection to re-target the circuit design to a different device. This information would be obtained by the designer by researching data books from each vendor to determine compatible devices and pin layouts. This can require considerable effort and is error prone. The designer would manually translate pin information to a constraints file but designs can have hundreds of pin locations. A further problem is that vendors have different signal name requirements that also need to be converted before a circuit design can be implemented onto a different logic device. The prior approach is time consuming and subject to error.
The present invention provides a method and system for transferring a circuit design from one logic device to another logic device that cures the above problems and others.
According to one embodiment of the present invention, a system for re-targeting a circuit design that was generated for a first programmable logic device to a second programmable logic device is provided. A compatibility logic identifies a second programmable logic device that is compatible with the first programmable logic device. A constraints file generator receives a report file configured for the first programmable logic device and translates the report file to a constraints file configured for the second programmable logic device such that the circuit design can be re-targeted on the second programmable logic device.
In accordance with a more limited aspect of the present invention, the system includes compatibility data that identifies compatibility characteristics between a plurality of programmable logic devices.
According to another embodiment of the present invention, a process of translating a circuit design targeted for a first programmable logic device to be targeted to a second programmable logic device is provided. A report file is received that identifies characteristics of the circuit design relating to the first programmable logic device. A second programmable logic device is then identified that is compatible with the first programmable device based on the characteristics from the report file. A constraints file is generated from the report file including pin constraints for the second programmable logic device that allows the circuit design to be targeted to the second programmable logic device.
In accordance with a more limited aspect of the present invention, the process includes providing device recommendations based on the compatibility of the second programmable logic device.
One advantage of the present invention is that the system can automatically generate a constraints file that allows a circuit design made for one logic device to be transferred to a compatible logic device.
Another advantage of the present invention is that the system can automatically identify compatible logic devices based on a report file.
Still further advantages of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description of the preferred embodiments.